`timescale 1ns / 1ns
module tb_aescontrol;
wire  keyexprdy,encdecrdy,keysel,rndkren,wrrndkrf,rconen;
wire  wrsben,mixsel,reginsel,wrregen,wrpckreg;
wire  [1:0] keyadsel;
wire  [3:0] krfaddr,wrsbaddr;
reg   clk = 1;
reg   rst,load,keyexp,staenc,stadec;
reg   [4:0] address;

aescontrol  aescontrol(clk,rst,load,address,keyexp,staenc,stadec,keyexprdy,encdecrdy,keysel,rndkren,wrrndkrf,krfaddr,rconen,wrsben,wrsbaddr,keyadsel,mixsel,reginsel,wrregen,wrpckreg);

//clock generation				   
initial clk = 1;
always #50 clk = ~clk;

initial 
	begin 
		#20  rst=1;//test reset.
		     load=0;
		     address=5'd0;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
		#200 rst=0;
		     load=1; //test load data.
		     address=5'd0;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
		#100 rst=0;
		     load=1;
		     address=5'd1;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
		#100 rst=0;
		     load=1;
		     address=5'd2;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
		#100 rst=0;
		     load=1;
		     address=5'd3;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
		#100 rst=0;
		     load=1;
		     address=5'd4;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
		#100 rst=0;
		     load=1;
		     address=5'd5;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		
     #100  rst=0;
		     load=1;
		     address=5'd6;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
	  #100  rst=0;
		     load=1;
		     address=5'd7;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
	  #100  rst=0;
		     load=1;
		     address=5'd8;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
	  #100  rst=0;
		     load=1;
		     address=5'd9;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
	  #100  rst=0;
		     load=1;
		     address=5'd10;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
	  #100  rst=0;
		     load=1;
		     address=5'd11;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
	  #100  rst=0;
		     load=1;
		     address=5'd12;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
	  #100  rst=0;
		     load=1;
		     address=5'd13;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
	  #100  rst=0;
		     load=1;
		     address=5'd14;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
	  #100  rst=0;
		     load=1;
		     address=5'd15;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
	  #100  rst=0;
		     load=1;
		     address=5'd16;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
	  #100  rst=0;
		     load=1;
		     address=5'd17;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
	  #100  rst=0;
		     load=1;
		     address=5'd18;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		        
      #100 rst=0;
		     load=1;
		     address=5'd19;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
	  #100  rst=0;
		     load=1;
		     address=5'd20;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
	  #100  rst=0;
		     load=1;
		     address=5'd21;
		     keyexp=0;
		     staenc=0;
		     stadec=0;
		     
	  #100  rst=0;
		     load=1;
		     address=5'd22;
		     keyexp=0;
		     staenc=0;
		     stadec=0;
     #100  rst=0;
		     load=1;
		     address=5'd23;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
	  #100  rst=0;
		     load=1;
		     address=5'd24;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
	  #100  rst=0;
		     load=1;
		     address=5'd25;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
	  #100  rst=0;
		     load=1;
		     address=5'd26;
		     keyexp=0;
		     staenc=0;
		     stadec=0;
     #100  rst=0;
		     load=1;
		     address=5'd27;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
	  #100  rst=0;
		     load=1;
		     address=5'd28;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
	  #100  rst=0;
		     load=1;
		     address=5'd29;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
	  #100  rst=0;
		     load=1;
		     address=5'd30;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
	  #100  rst=0;
		     load=1;
		     address=5'd31;
		     keyexp=0;
		     staenc=0;
		     stadec=0;		     
	  #100  rst=0;
		     load=0;
		     address=5'd0;
		     keyexp=1;//test cipher key expansion.
		     staenc=0;
		     stadec=0;		     
	  #100  rst=0;
		     load=0;
		     address=5'd1;
		     keyexp=0;
		     staenc=0;
		     stadec=0;

	  #1200 rst=0;
		     load=0;
		     address=5'd2;
		     keyexp=0;
		     staenc=1;//test start encryption.
		     stadec=0;		     
	  #100  rst=0;
		     load=0;
		     address=5'd3;
		     keyexp=0;
		     staenc=0;
		     stadec=0;

	  #1200 rst=0;
		     load=0;
		     address=5'd16;
		     keyexp=0;
		     staenc=0;
		     stadec=1;//tset start decryption.		     
	  #100  rst=0;
		     load=0;
		     address=5'd17;
		     keyexp=0;
		     staenc=0;
		     stadec=0;
             
	  #1200 $finish;		  
	end					
endmodule
